Quadruple SRAM
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 The S7Q163662M and S7Q161862M are 18,874,368-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7Q163662M and 1,048,576 words by 18bits for S7Q161862M. The Quadruple operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K, and transferred out of SRAM on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn around. Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and write operations. Synchronous pipeline read and early write enable high speed operations. Simple depth expansion is accomplished by using R and W for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system. The S7Q163662M and S7Q161862M are implemented with Netsol's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

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